Communication Architectures for Systems-on-Chip by José L. Ayala

By José L. Ayala

A presentation of cutting-edge ways from an business purposes point of view, Communication Architectures for Systems-on-Chip indicates pros, researchers, and scholars easy methods to assault the matter of information verbal exchange within the manufacture of SoC architectures.

With its lucid representation of present developments and study bettering the functionality, caliber, and reliability of transactions, this can be a vital reference for somebody facing verbal exchange mechanisms for embedded platforms, systems-on-chip, and multiprocessor architectures—or attempting to conquer latest boundaries. Exploring architectures at present carried out in synthetic SoCs—and these being proposed—this booklet analyzes a variety of functions, including:

  • Well-established communique buses
  • Less universal networks-on-chip
  • Modern applied sciences that come with using carbon nanotubes (CNTs)
  • Optical hyperlinks used to hurry up facts move and develop either safety and caliber of provider (QoS)

The book’s participants pay particular recognition to more recent difficulties, together with the way to guard transactions of serious on-chip info (personal facts, safeguard keys, etc.) from an exterior assault. They research mechanisms, revise verbal exchange protocols concerned, and study total impression on procedure performance.

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Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 46 46 49 50 50 51 51 51 52 54 55 56 58 60 60 62 62 63 64 64 65 67 68 68 70 70 73 75 76 79 Introduction With powerful embedded devices populating the consumer electronics market, Multiprocessor Systems-on-Chip (MPSoCs) are the most promising way to keep on exploiting the high level of integration provided by the semiconductor technology while, at the same time, satisfying the constraints imposed by the embedded system market in terms of performance and power consumption.

2 Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 IBM’s CoreConnect . . . . . . . . . . . . . . . . . . . 2 Extensible Processing Platform . . . . . . . . . . . . . Open Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introducing the OCP-IP . . . . . . . . . . . . . . . . . . . . . 2 Specification .

FPGA On-Chip Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Altera: Avalon . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 IBM’s CoreConnect . . . . . . . . . . . . . . . . . . . 2 Extensible Processing Platform . . . . . . . . . . . . . Open Standards . . . . . . . . .

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